In some digital devices, a set of registers is used to store values that determine how the device is configured, and how the device should operate. For example, a PCI bus interface uses resettable configuration space registers. From time to time it is necessary to reset the registers to a known "reset" value, for example, at cold start, or after a failure.
Typically, resettable registers operate as follows. Initially, the registers store the known reset value. During operation, other values can be written to the registers. After a reset, a read access to a particular register should produce the reset value, until the register has been written. After valid data has been written to a register, the registers can be read. In most cases, the reset is performed to all registers in a single time unit, for example, one cycle of the system clock.
Prior art approaches use resettable registers directly. A reset capability adds to the amount of circuitry required to implement a storage location. In some implementation technologies, particularly those relying on a restricted set of pre-diffused circuit structures, for example mask or field programmed gate arrays, (FPGA), the number of additional circuit elements needed to provide a reset capability can be substantial.
Therefore, there is a need for memories that can be reset to produce known values after a reset without substantially increasing the number of circuit elements.